----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:33:59 03/14/2012 
-- Design Name: 
-- Module Name:    serial_input - gedragbeschrijving 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;


library work;
use work.UART_RAM.ALL;
use work.RAMTORAM.all;
--use work.UART_RX_Pack.all;
use work.read_uart_ram_p.all;
use work.parity.all;
use WORK.UART_PACK.all;


-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity serial_in is
    Port ( serial_input : in  STD_LOGIC;
           clk_50MHz : in  STD_LOGIC;
           ID_RAMDATA : out  STD_LOGIC_VECTOR (5 downto 0);
           ID_RAMADDR : out  STD_LOGIC_VECTOR (7 downto 0);
           ID_RAMENWR : out  STD_LOGIC;
           baud_clk : out  STD_LOGIC);
end serial_in;

architecture structuur of serial_in is

signal write_en : std_logic;
signal reset_parity_sig, done_sig, check_sig, read_uart_ram, write_16x8_sig, buffer_full_sig, data_present_sig, reset_buffer_sig, read_buffer_sig : std_logic;
signal uart_data_sig, parity_sig : std_logic_vector (7 downto 0);
signal ram16x8addr_sig : std_logic_vector ( 3 downto 0);
signal ram16x8data_sig : std_logic_vector (7 downto 0);
signal read16x8data_sig, read16x8pardata_sig : std_logic_vector (7 downto 0);
signal read16x8addr_sig, read16x8paraddr_sig : std_logic_vector (3 downto 0);
 



begin
	RAMCOPY: Uartverwerking PORT MAP(
		clk_50MHz => clk_50MHz,
		done => check_sig,
		reset_parity => reset_parity_sig,
		READ_RAM16x8data => Read16x8data_sig,
		READ_RAM16x8addr => read16x8addr_sig,
		Write_idram_en => ID_RAMENWR,
		write_idram_data => ID_RAMDATA,
		Write_idram_addr => ID_RAMADDR
	);

	UART_RAM_16x8: RAM_16x8 PORT MAP(
		Clk => clk_50MHz,
		Write_En => write_16x8_sig,
		Write_ADDR => ram16x8addr_sig,
		Read_ADDR => read16x8addr_sig,
		Read_ADDR_2 => read16x8paraddr_sig,
		Write_DATA => ram16x8data_sig,
		Read_DATA => read16x8data_sig,
		Read_DATA_2 => read16x8pardata_sig
	);

	FIFO_to_UART_RAM: Read_UART_RAM PORT MAP(
		Data_in => uart_data_sig,
		Reset => '0',
		Klok => clk_50MHz,
		Buffer_full => buffer_full_sig,
		Data_present => data_present_sig,
		read_buffer => read_buffer_sig,
		Write_RAM => write_16x8_sig,
		Done => done_sig,
		Adres_RAM => ram16x8addr_sig,
		Data_RAM => ram16x8data_sig 
	);

	UART_RXTX_comp: totaal_uart PORT MAP(
		RX_serial_in => serial_input,
		RX_data_out => uart_data_sig,
		RX_read_buffer => read_buffer_sig,
		RX_reset_buffer => reset_buffer_sig,
		RX_buffer_data_present => data_present_sig,
		RX_buffer_full => buffer_full_sig,
		RX_buffer_half_full => open,
		TX_data_in => (others => '0'),
		TX_write_buffer => '0',
		TX_reset_buffer => '0',
		TX_serial_out => open,
		TX_buffer_full => open,
		TX_buffer_half_full => open,
		clk => clk_50MHz
	);


	parity_controle: parity_controle PORT MAP(
		klok => clk_50MHz,
		enable => Done_sig,
		reset => '0',
	--	Write_En_out => open,
		datapaket => read16x8pardata_sig,
	--	vorig_parity => parity_sig,
	--	parity => parity_sig,
		teller_out => read16x8paraddr_sig,
		parity_oke => check_sig
	);


	end structuur;
	
library ieee;
use ieee.std_logic_1164.all;

package serial_in_package is

component serial_in is
    Port ( serial_input : in  STD_LOGIC;
           clk_50MHz : in  STD_LOGIC;
           ID_RAMDATA : out  STD_LOGIC_VECTOR (5 downto 0);
           ID_RAMADDR : out  STD_LOGIC_VECTOR (7 downto 0);
           ID_RAMENWR : out  STD_LOGIC;
           baud_clk : out  STD_LOGIC);
end component;
end package;

